1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device and more particularly, a process for fabricating a high-speed bipolar transistor which operates even in the region for very high frequency.
2. Description of the Related Art
Generally, to enhance the performance of integrated circuts (IC), it is important to reduce the power consumption there of in addition to increasing the operating speed. To the end, it is necessary that the individual elements in the IC must be reduced in minimum size as possible as and more fast in the operation speed.
Among the IC, particularly, a bipolar transistor which is used commonly for systems requiring a high speed of operation, for example, a central processing unit, a communicating system, etc. needs further improvements in the size of the element itself and in the operating speed as well as in the power consumption.
In the prior art, isolation method by means of P-N junction region which has been mainly used to produce bipolar IC involves a lot of restrictions in the reduction of the size of the element because the influence due to lateral diffusion, the existence of depletion region and the likes should be taken into account. Accordingly, it was difficult to expect a desired results in view of the operating speed and the power consumption because the reduction of resistance component and capacitance component which exist in the element itself is restricted to a certain limitted extent.
Another prior art isolation method developed recently to solve such a problem as mentioned here in above, as shown in FIG. 2, uses a combination method of an element isolation method by means of oxide layer(SiO.sub.2), and other method which is accomplished by forming a self-aligned structure of emitter(22) and base(24) by means of polysilicon layer(21), the transistor fabricated in this way is so-called PSA (polysilicon self-aligned) transistor.
Where the transistor is fabricated by this method, the size of element is reducible to a desirable extent, and emitter region(22) and base region(24) can be made in shallow junction.
Accordingly, the resistance component and the capacitance component which exist in the element are also reducible to a desire extent, thus obtaining advantages in all respects including operating speed, power consumption, packing density, etc.
FIG. 2 shows the cross sectional view of biplar NPN transistor produced by the PSA method.
In producing the PSA bipolar NPN transistor whose emitter region and base region are self-aligned by a polysilicon, to eliminate a series resistance component which exists in the base region, P.sup.+ -type extrinsic base region which has high impurity concentration as a portion(23) shown in FIG. 2 must be provided between P.sup.- -type intrinsic base region and P.sup.- -type polysilicon layer which acts a role as an exterior conductive line of the base.
However, where the area of P.sup.+ -type extrinsic base region is large, the capacitance component increases since minority carrier storage produced in this portion becomes larger, so that the operating speed is decreased.
There was provided with a transistor produced by means of a method newly developed to solve the above problem. As shown in FIG. 3, it assumes a form where P.sup.+ -type extrinsic base region(33) which has a width of 4000 to 6000 .ANG. is provided by overeching the 1500 .ANG.-thick oxide layer(32) in the lower part of polysilicon layer(31) to the extent of 4000 to 6000 .ANG. using a wet etching process, filling it up with P.sup.+ -type polysilicone using a low pressure chemical vapor deposition (LPCVD) and then annealing it.
Although the bipolar NPN transistor made in this manner introduces a marked impovement upon the operating speed; it is difficult to adjust the process condition because the width of P.sup.+ -type extrinsic base region is determined by wet etching.
Further, since the process for fabricating the NPN transistor is conducted in the state that a portion in which emitter is to be formed is exposed, the surface of the exposed portion may suffer damage during the progress of process, particularly, in the stage of dry etching and the electrical property thereof may become worse.
The object of the present invention is to provide a process for fabricating a high-performance semiconductor device which has eliminated the aforementioned problem.
The other object of the present invention is to provide a process for fabricating a semiconductor device having features which are a high speed of operation, a minimum size and a small power consumption.
The further object of the instant invention is to provide a process for fabricating a semiconductor device characterized by a protection of a portion in the surface of the substrate, which is provided the operation region of transistor, with polysilicon layer from damages.